1. Field of the Invention
The present invention relates to electrically erasable ("E.sup.2 ") non-volatile memory cells. In particular, the present invention relates to the design and testing of E.sup.2 non-volatile memory cells in a programmable integrated circuit.
2. Discussion of the Related Art
FIG. 1 is a schematic circuit of a typical E.sup.2 cell 100 used as a non-volatile configuration fuse. Such a configuration fuse, for example, can be used to configure a programmable logic circuit ("PLD"). As shown in FIG. 1, E.sup.2 cell 100 includes a storage transistor device 101 with a floating gate electrode which is also the gate electrode of sense transistor 102. Storage transistor device 101 is programmed or erased during "programming mode", and read during "user mode". During programming mode, to erase storage transistor device 100, storage transistor device 101 is selected by raising the voltage at the gate terminal 108 of NMOS transistor 115 to a voltage approximately equal to (V.sub.CC -V.sub.TN), where V.sub.CC and V.sub.TN are the supply voltage and the threshold voltage of an NMOS transistor, respectively. At the same time, terminal 107 (a bit line) is grounded and terminal 110 is raised to a high programming voltage (V.sub.pp) to place negative charges onto the floating gate. Conversely, to program storage transistor device 101, storage transistor device 101 is selected by raising the voltage at the gate terminal 108 of NMOS transistor 115 to a voltage approximately equal to (V.sub.pp +V.sub.TN). At the same time, terminal 107 (bit line) is raised to a high programming voltage, and terminal 110 is grounded to drain negative charges from the floating gate. The programming and erase times of E.sup.2 cell 100 can each be as much as 20 milliseconds.
During programming mode, to verify the content of storage transistor device 101, storage transistor device 101 is selected by providing, respectively, a voltage ground at terminal 108 and a logic high voltage at terminal 109. Terminal 109 is coupled to the gate terminal of NMOS transistor 103. Gate terminal 114 of NMOS transistor 111 is also provided a voltage of V.sub.CC. During verify, the bit line (i.e., terminal 107) is pulled up to a logic high voltage by a small current reference and sensed. If storage transistor device 101 is programmed, NMOS transistor 102 is conducting (i.e., the voltage at the gate terminal of NMOS transistor 102 is positive), thus pulling the voltage at terminal 116 to ground. Inverter 105 thus provides a logic high voltage at output terminal 106. Since terminal 106 is at a logic high voltage, conducting transistors 111 and 112 pull terminal 107 down. Conversely, if storage transistor device 101 is erased, transistor 102 is not conducting. Transistor 104, which receives the bias voltage "Biasp" at gate terminal 113, pulls terminal 116 to a logic high voltage. Consequently, inverter 105 provides a logic low voltage at terminal 106. Thus, the voltage at terminal 107 is not pulled down.
To read the content of storage transistor device 101, storage transistor device 101 is selected by providing a logic high voltage at terminal 109, which is coupled to the gate terminal of NMOS transistor 103. Drain terminal 116 of transistor 103 is coupled to the drain terminal of PMOS transistor 104, which receives a bias voltage "Biasp" at its gate terminal 113. If storage transistor device 101 is programmed, NMOS transistor 102 is conducting (i.e., the voltage at the gate terminal of NMOS transistor 102 is positive), thus pulling the voltage at terminal 116 to ground. Inverter 105 thus provides a logic high voltage at output terminal 106, indicating that storage transistor device 101 is programmed. Conversely, if storage transistor device 101 is erased, transistor 102 is not conducting. Transistor 104, which receives the bias voltage Biasp at gate terminal 113, pulls terminal 116 to a logic high voltage. Consequently, inverter 105 provides a logic low voltage at terminal 106 to indicate that storage transistor device 101 is erased.
One drawback of E.sup.2 cell 100 is, when storage transistor cell 101 is programmed, a current which is drawn through PMOS transistor 104 and NMOS transistors 102 and 103 during a read operation. Although this current is limited to a few microamps by the bias voltage at terminal 113, the current can be significant when a large number of E.sup.2 cells exist in a programmable integrated circuit.
Another drawback of E.sup.2 cell 100 relates to the long programming and erasing times. To perform a function test of a circuit implemented in the programmable integrated circuit, it is often necessary to change the programmed or erased states of multiple E.sup.2 cells multiple times. For example, in a demultiplexer circuit which demultiplexes a data bus to twenty data destinations, the E.sup.2 cells that configure the demultiplexer will each have to be programmed or erased more than twenty times. The time required for such a functional test can become prohibitively long.